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1 typical a pplica t ion fea t ures descrip t ion timerblox: long timer, low frequency oscillator the lt c ? 6995 is a silicon oscillator with a programmable period range of 1.024ms to 9.54 hours (29.1hz to 977 hz), specifically intended for long duration timing events. the ltc6995 is part of the timerblox ? family of versatile silicon timing devices. a single resistor, r set , programs the ltc6995s internal master oscillator frequency. the output clock period is determined by this master oscillator and an internal frequency divider, n div , programmable to eight settings from 1 to 2 21 . t out = n div ?r set 50k ? ?1.024ms, n div = 1,8,64,...,2 21 when oscillating, the ltc6995 generates a 50% duty cycle square wave output. a reset function is provided to stop the master oscillator and clear internal dividers. removing reset initiates a full output clock cycle which is useful for programmable power-on reset and watchdog timer applications. the ltc6995 has two versions of reset functionality. the reset input is active high for the LTC6995-1 and active low for the ltc6995-2. the polarity of the output when reset is selectable for both versions. output (oscillator start state) rst/rst polarity LTC6995-1 ltc6995-2 0 0 oscillating (low) 0 (reset) 1 0 0 (reset) oscillating (low) 0 1 oscillating (high) 1 (reset) 1 1 1 (reset) oscillating (high) a pplica t ions n period range: 1ms to 9.5 hours n timing reset by power-on or reset input n configured with 1 to 3 resistors n <1.5% maximum frequency error n programmable output polarity n 2.25v to 5.5v single supply operation n 55a to 80a supply current (2 ms to 9.5hr clock period) n 500 s start-up time n cmos output driver sources/sinks 20ma n C55 c to 125c operating temperature range n available in low profile (1mm) sot-23 (thinsot?) and 2mm 3mm dfn packages n power-on reset timer n long time one shot n heartbeat timers n watchdog timers n periodic wake-up call n high vibration, high acceleration environments l, lt , lt c , lt m , linear technology, timerblox and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. active low power-on reset timer LTC6995-1 0.1f out 1m 392k 118k rst gnd set out v + div v + v + 699512 ta01 5 seconds 1/2 t out timer stopped power-on reset (1ms to 4.8 hours) 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
2 a bsolu t e maxi m u m r a t ings supply voltage (v + ) to gnd ........................................ 6 v maximum voltage on any pin ................ ( gnd C 0.3 v) v pin (v + + 0.3 v) operating temperature range ( note 2) ltc 69 95 c ............................................ C4 0 c to 85 c ltc 69 95 i ............................................. C 40 c to 85 c ltc 69 95 h .......................................... C4 0 c to 125 c ltc 69 95 mp ....................................... C 55 c to 125 c (note 1) o r d er i n f or m a t ion p in c on f igura t ion specified temperature range ( note 3) ltc 69 95 c ................................................ 0 c to 70 c ltc 69 95 i ............................................. C 40 c to 85 c ltc 69 95 h .......................................... C4 0 c to 125 c ltc 69 95 mp ....................................... C 55 c to 125 c junction temperature ........................................... 15 0 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) s6 package ........................................................... 30 0 c lead free finish tape and reel (mini) tape and reel part marking* package description specified temperature range ltc6995cdcb-1#trmpbf ltc6995cdcb-1#trpbf lgjm 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6995idcb-1#trmpbf ltc6995idcb-1#trpbf lgjm 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6995hdcb-1#trmpbf ltc6995hdcb-1#trpbf lgjm 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6995cdcb-2#trmpbf ltc6995cdcb-2#trpbf lgjp 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6995idcb-2#trmpbf ltc6995idcb-2#trpbf lgjp 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6995hdcb-2#trmpbf ltc6995hdcb-2#trpbf lgjp 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6995cs6-1#trmpbf ltc6995cs6-1#trpbf ltgjn 6-lead plastic tsot-23 0c to 70c ltc6995is6-1#trmpbf ltc6995is6-1#trpbf ltgjn 6-lead plastic tsot-23 C40c to 85c ltc6995hs6-1#trmpbf ltc6995hs6-1#trpbf ltgjn 6-lead plastic tsot-23 C40c to 125c ltc6995mps6-1#trmpbf ltc6995mps6-1#trpbf ltgjn 6-lead plastic tsot-23 C55c to 125c ltc6995cs6-2#trmpbf ltc6995cs6-2#trpbf ltgjq 6-lead plastic tsot-23 0c to 70c ltc6995is6-2#trmpbf ltc6995is6-2#trpbf ltgjq 6-lead plastic tsot-23 C40c to 85c ltc6995hs6-2#trmpbf ltc6995hs6-2#trpbf ltgjq 6-lead plastic tsot-23 C40c to 125c ltc6995mps6-2#trmpbf ltc6995mps6-2#trpbf ltgjq 6-lead plastic tsot-23 C55c to 125c trm = 500 pieces. * temperature grades are identified by a label on the shipping container. consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ LTC6995-1/ltc6995-2 LTC6995-1/ltc6995-2 top view out gnd rst/ rst v + div set dcb package 6-lead (2mm 3mm) plastic dfn 4 5 7 gnd 6 3 2 1 t jmax = 150c, ja = 64c/w, jc = 9.6c/w exposed pad ( pin 7) connected to gnd, pcb connection op tional rst/ rst 1 gnd 2 set 3 6 out 5 v + 4 div top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 192c/w, jc = 51c/w 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. test conditions are v + = 2.25v to 5.5v, rst = 0v for LTC6995-1, rst = v + for ltc6995-2, divcode = 0 to 15 (n div = 1 to 2 21 ), r set = 50k to 800k, r load = 5k, c load = 5pf unless otherwise noted. symbol parameter conditions min typ max units t out output clock period 1.024m 34,360 seconds f out output frequency 29.1 977 hz ?f out frequency accuracy (note 4) 29.1hz f out 977hz l 0.8 1.5 2.2 % % ? f out /?t frequency drift over temperature l 0.005 %/c ?f out /?v + frequency drift over supply v + = 4.5v to 5.5v v + = 2.25v to 4.5v l l 0.23 0.06 0.55 0.16 %/ v %/v long-t erm frequency stability (note 11) 90 ppm/khr period jitter (note 10) n div = 1 n div = 8 15 7 ppm rms ppm rms bw frequency modulation bandwidth 0.4 ? f out hz t s frequency change settling time (note 9) 1 cycle analog inputs v set voltage at set pin l 0.97 1.00 1.03 v ?v set /?t v set drift over temperature l 75 v/c r set frequency-setting resistor l 50 800 k v div div pin voltage l 0 v + v ?v div /?v + div pin valid code range (note 5) deviation from ideal v div /v + = (divcode + 0.5)/16 l 1.5 % div pin input current l 10 na power supply v + operating supply voltage range l 2.25 5.5 v power-on reset voltage l 1.95 v i s supply current r l = , r set = 50k v + = 5.5v v + = 2.25v l l 135 105 170 135 a a r l = , r set = 100k v + = 5.5v v + = 2.25v l l 100 80 130 105 a a r l = , r set = 800k v + = 5.5v v + = 2.25v l l 65 55 100 85 a a r l = , i set = 0a v + = 5.5v v + = 2.25v 60 52 a a 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
4 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. test conditions are v + = 2.25v to 5.5v, rst = 0v for LTC6995-1, rst = v + for ltc6995-2, divcode = 0 to 15 (n div = 1 to 2 21 ), r set = 50k to 800k, r load = , c load = 5pf unless otherwise noted. symbol parameter conditions min typ max units digital i/o rst pin input capacitance 2.5 pf rst pin input current rst = 0v to v + 10 na v ih high level rst pin input voltage (note 6) l 0.7 ? v + v v il low level rst pin input voltage (note 6) l 0.3 ? v + v i out(max) output current v + = 2.7v to 5.5v 20 ma v oh high level output voltage (note 7) v + = 5.5v i out = C1ma i out = C16ma l l 5.45 4.84 5.48 5.15 v v v + = 3.3v i out = C1ma i out = C10ma l l 3.24 2.75 3.27 2.99 v v v + = 2.25v i out = C1ma i out = C8ma l l 2.17 1.58 2.21 1.88 v v v ol low level output voltage (note 7) v + = 5.5v i out = 1ma i out = 16ma l l 0.02 0.26 0.04 0.54 v v v + = 3.3v i out = 1ma i out = 10ma l l 0.03 0.22 0.05 0.46 v v v + = 2.25v i out = 1ma i out = 8ma l l 0.03 0.26 0.07 0.54 v v t rst reset propagation delay v + = 5.5v v + = 3.3v v + = 2.25v 16 24 40 ns ns ns t width minimum input pulse width v + = 3.3v 5 ns t r output rise time (note 8) v + = 5.5v v + = 3.3v v + = 2.25v 1.1 1.7 2.7 ns ns ns t f output fall time (note 8) v + = 5.5v v + = 3.3v v + = 2.25v 1.0 1.6 2.4 ns ns ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6995c is guaranteed functional over the operating temperature range of C40c to 85c. note 3: the ltc6995c is guaranteed to meet specified performance from 0c to 70c. the ltc6995c is designed, characterized and expected to meet specified performance from C40c to 85c but it is not tested or qa sampled at these temperatures. the ltc6995i is guaranteed to meet specified performance from C40c to 85c. the ltc6995h is guaranteed to meet specified performance from C40c to 125c. the ltc6995mp is guaranteed to meet specified performance from C55c to 125c. note 4: frequency accuracy is defined as the deviation from the f out equation, assuming r set is used to program the frequency. note 5: see operation section, table 1 and figure 2 for a full explanation of how the div pin voltage selects the value of divcode. note 6: the rst pin has hysteresis to accommodate slow rising or falling signals. the threshold voltages are proportional to v + . typical values can be estimated at any supply voltage using v rst(rising) 0.55 ? v + + 185mv and v rst(falling) 0.48 ? v + C 155mv. note 7: to conform to the logic ic standard, current out of a pin is arbitrarily given a negative value. note 8: output rise and fall times are measured between the 10% and the 90% power supply levels with 5pf output load. these specifications are based on characterization. note 9: settling time is the amount of time required for the output to settle within 1% of the final frequency after a 0.5 or 2 change in i set . note 10: jitter is the ratio of the deviation of the period to the mean of the period. this specification is based on characterization and is not 100% tested. note 11: long-term drift of silicon oscillators is primarily due to the movement of ions and impurities within the silicon and is tested at 30c under otherwise nominal operating conditions. long-term drift is specified as ppm/khr due to the typically nonlinear nature of the drift. to calculate drift for a set time period, translate that time into thousands of hours, take the square root and multiply by the typical drift number. for instance, a year is 8.77khr and would yield a drift of 266ppm at 90ppm/khr. drift without power applied to the device may be approximated as 1/10th of the drift with power, or 9ppm/ khr for a 90ppm/khr device. 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
5 typical p er f or m ance c harac t eris t ics frequency error vs r set frequency drift vs supply voltage typical v set distribution v set drift vs i set v set drift vs supply v set vs temperature frequency error vs temperature frequency error vs temperature frequency error vs temperature v + = 3.3v, r set = 200k, t a = 25c unless otherwise noted. v set (v) 0.98 0 100 50 150 200 250 0.996 1.004 1.012 1.02 0.988 699512 g06 number of units 2 lots dfn and sot-23 1274 units i set (a) 0 ?1.0 0 0.4 0.2 0.6 0.8 1.0 10 15 20 ?0.4 ?0.2 ?0.6 ?0.8 5 699512 g07 v set (mv) referenced to i set = 10a supply (v) 2 ?1.0 0 0.4 0.2 0.6 0.8 1.0 4 5 6 ?0.4 ?0.2 ?0.6 ?0.8 3 699512 g08 drift (mv) referenced to v + = 4v temperature (c) ?50 0.980 1.000 1.010 1.005 1.015 1.020 0 25 50 100 125 0.995 0.990 0.985 ?25 75 699512 g09 v set (v) 3 parts temperature (c) ?50 error (%) 1 2 3 25 75 699512 g01 0 ?1 ?25 0 50 100 125 ?2 ?3 guaranteed max over temperature guaranteed min over temperature r set = 50k 3 parts temperature (c) ?50 error (%) 1 2 3 25 75 699512 g02 0 ?1 ?25 0 50 100 125 ?2 ?3 guaranteed max over temperature guaranteed min over temperature r set = 200k 3 parts temperature (c) ?50 error (%) 1 2 3 25 75 699512 g03 0 ?1 ?25 0 50 100 125 ?2 ?3 guaranteed max over temperature guaranteed min over temperature r set = 800k 3 parts r set (k) 0 ?3 error (%) ?2 ?1 0 1 2 3 3 parts 200 400 600 800 699512 g04 guaranteed max over temperature guaranteed min over temperature supply voltage (v) 2 ?0.5 drift (%) ?0.4 ?0.2 ?0.1 0 0.5 0.2 3 4 699512 g05 ?0.3 0.3 0.4 0.1 5 6 referenced to v + = 4.5v r set = 50k r set = 200k r set = 800k 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
6 supply current vs r set rst threshold voltage vs supply voltage typical i set current limit vs v + supply current vs supply voltage supply current vs temperature supply current vs rst pin voltage reset propagation delay (t rst ) vs supply voltage rise and fall time vs supply voltage typical p er f or m ance c harac t eris t ics v + = 3.3v, r set = 200k, t a = 25c unless otherwise noted. supply voltage (v) 2 0 power supply current (a) 25 50 75 100 125 150 3 4 5 6 699512 g10 r set = 50k r set = 100k r set = 200k r set = 800k temperature (c) ?50 power supply current (a) 100 125 150 25 75 699512 g11 75 50 ?25 0 50 100 125 25 0 5v, r set = 100k 2.5v, r set = 100k 2.5v, r set = 800k 5v, r set = 800k v rst /v + (v/v) 0 power supply current (a) 150 200 250 0.8 699512 g12 100 50 0 0.2 0.4 0.6 1.0 5v rst falling 5v rst rising 3.3v rst falling 3.3v rst rising r set = 800k r set (k) 0 0 power supply current (a) 25 50 75 100 125 150 200 400 600 800 699512 g13 v + = 5v v + = 3.3v v + = 2.5v supply voltage (v) i set (a) 699512 g14 1000 400 800 200 600 0 2 4 3 5 6 set pin shorted to gnd supply voltage (v) rst pin voltage (v) 699512 g15 3.5 1.0 2.0 3.0 0.5 1.5 2.5 0 2 4 3 5 6 positive-going negative-going supply voltage (v) 2 0 propagation delay (ns) 5 15 20 25 50 35 3 4 699512 g16 10 40 45 30 5 6 c load = 5pf supply voltage (v) rise/fall time (ns) 699512 g17 3.0 1.5 2.5 1.0 0.5 2.0 0 2 4 3 5 6 c load = 5pf t rise t fall typical frequency error vs time (long-term drift) time (h) delta frequency (ppm) 699512 g18 50 0 150 ?150 ?100 ?50 100 200 ?200 0 1200 400 800 1600 2000 2400 2800 65 units sot-23 and dfn parts t a = 30c 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
7 output resistance vs supply current typical LTC6995-1 start-up with pol = 1 typical p er f or m ance c harac t eris t ics v + = 3.3v, r set = 200k, t a = 25c unless otherwise noted. supply voltage (v) output resistance () 699512 g19 50 25 20 35 45 5 10 15 30 40 0 2 4 3 5 6 output sourcing current output sinking current v + 5v/div out 5v/div rst 5v/div 5ms/div v + = 5v divcode = 15 r set = 499k 699512 g20 4ms start-up output reset reset released, 100hz output clock p in func t ions (dcb/s6) v + (pin 1/pin 5): supply voltage (2.25 v to 5.5 v). this sup- ply should be kept free from noise and ripple. it should be bypassed directly to the gnd pin with a 0.1f capacitor. div ( pin 2/pin 4): programmable divider and polarity input. an internal a/d converter ( referenced to v + ) moni- tors the div pin voltage (v div ) to determine a 4- bit result (divcode). v div may be generated by a resistor divider between v + and gnd. use 1% resistors to ensure an ac- curate result . the div pin and resistors should be shielded from the out pin or any other traces that have fast edges. limit the capacitance on the div pin to less than 100pf so that v div settles quickly. the msb of divcode (pol) determines the polarity of the out pin. set (pin 3/pin 3): frequency-setting input. the voltage on the set pin (v set ) is regulated to 1 v above gnd. the amount of current sourced from the set pin (i set ) pro- grams the master oscillator frequency. the i set current range is 1.25 a to 20 a. the output oscillation will stop if i set drops below approximately 500 na. a resistor con- nected between set and gnd is the most accurate way to set the frequency. for best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/c or better temperature coefficient. for lower ac - curacy applications an inexpensive 1% thick film resistor may be used. limit the capacitance on the set pin to less than 10pf to minimize jitter and ensure stability. capacitance less than 100 pf maintains the stability of the feedback circuit regulating the v set voltage. 699512 pf LTC6995-1/ ltc6995-2 rst gnd set out v + div c1 0.1f r set r2 r1 v + rst or rst (pin 4/pin 1): output reset. the reset input is used to stop the output oscillator and to clear internal dividers. when reset is released the oscillator starts with a full half period time interval. the output logic state when reset is determined by the programmed divcode. the LTC6995-1 has an active high rst input. the ltc6995-2 has an active low rst input. 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
8 b lock diagra m (s6 package pin numbers shown) 699512 bd programmable divider fixed divider 1024 divider reset 1, 8, 64, 512 4096, 2 15 , 2 18 , 2 21 master oscillator por output polarity digital filter 4-bit a/d converter pol bit r1 r2 div v + out 5 4 1 6 halt oscillator output if i set < 500na mclk t master = 1s 50k v set i set + ? i set i set v set = 1v + ? 1v 3 22 gnd set rst ltc6995-2 only r set t out p in func t ions (dcb/s6) gnd (pin 5/pin 2): ground. tie to a low inductance ground plane for best performance. out (pin 6/pin 6): oscillator output. the out pin swings from gnd to v + with an output resistance of approximately 30. when driving an led or other low impedance load a series output resistor should be used to limit source/ sink current to 20ma. 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
9 o pera t ion the ltc6995 is built around a master oscillator with a 1mhz maximum frequency. the oscillator is controlled by the set pin current (i set ) and voltage (v set ), with a 1mhz ? 50 k conversion factor that is accurate to 0.8% under typical conditions. f master = 1 t master = 1mhz ? 50k ? ? i set v set a feedback loop maintains v set at 1v 30 mv, leaving i set as the primary means of controlling the output frequency. the simplest way to generate i set is to connect a resistor (r set ) between set and gnd, such that i set = v set /r set . the master oscillator equation reduces to: f master = 1 t master = 1mhz ? 50k ? r set from this equation, it is clear that v set drift will not affect the output frequency when using a single program resistor (r set ). error sources are limited to r set tolerance and the inherent frequency accuracy ?f out of the ltc6995. r set may range from 50 k to 800k ( equivalent to i set between 1.25a and 20a). before reaching the out pin, the oscillator frequency passes through a fixed 1024 divider. the ltc6995 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 2 15 , 2 18 or 2 21 . the divider ratio n div is set by a resistor divider attached to the div pin. f out = 1mhz ? 50k ? 1024 ?n div ? i set v set , or t out = 1 f out = n div 50k ? ? v set i set ?1.024ms with r set in place of v set /i set the equation reduces to: t out = n div ?r set 50k ? ?1.024ms divcode the div pin connects to an internal, v + referenced 4-bit a/d converter that determines the divcode value. divcode programs two settings on the ltc6995: 1. divcode determines the output frequency divider set - ting, n div . 2. divcode determines the polarity of the rst and out pins, via the pol bit. v div may be generated by a resistor divider between v + and gnd as shown in figure 1. figure 1. simple technique for setting divcode 699512 f01 ltc6995 v + div gnd r1 r2 2.25v to 5.5v table 1 offers recommended 1% resistor values that ac- curately produce the correct voltage division as well as the corresponding n div and pol values for the recommended resistor pairs. other values may be used as long as: 1. the v div /v + ratio is accurate to 1.5% ( including resis- tor tolerances and temperature effects) 2. the driving impedance ( r 1||r 2) does not exceed 500k . if the voltage is generated by other means ( i.e., the output of a dac) it must track the v + supply voltage. the last column in table 1 shows the ideal ratio of v div to the supply voltage, which can also be calculated as: v div v + = divcode + 0.5 16 1.5% for example, if the supply is 3.3 v and the desired divcode is 4, v div = 0.281 ? 3.3v = 928mv 50mv. figure 2 illustrates the information in table 1, showing that n div is symmetric around the divcode midpoint. 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
10 o pera t ion table 1. divcode programming divcode pol n div recommended t out r1 (k) r2 (k) v div /v + 0 0 1 1.024ms to 16.384ms open short 0.03125 0.015 1 0 8 8.192ms to 131ms 976 102 0.09375 0.015 2 0 64 65.5ms to 1.05sec 976 182 0.15625 0.015 3 0 512 524ms to 8.39sec 1000 280 0.21875 0.015 4 0 4,096 4.19sec to 67.1sec 1000 392 0.28125 0.015 5 0 32,768 33.6sec to 537sec 1000 523 0.34375 0.015 6 0 262,144 268sec to 4,295sec 1000 681 0.40625 0.015 7 0 2,097,152 2,147sec to 34,360sec 1000 887 0.46875 0.015 8 1 2,097,152 2,147sec to 34,360sec 887 1000 0.53125 0.015 9 1 262,144 268sec to 4,295sec 681 1000 0.59375 0.015 10 1 32,768 33.6sec to 537sec 523 1000 0.65625 0.015 11 1 4,096 4.19sec to 67.1sec 392 1000 0.71875 0.015 12 1 512 524ms to 8.39sec 280 1000 0.78125 0.015 13 1 64 65.5ms to 1.05sec 182 976 0.84375 0.015 14 1 8 8.192ms to 131ms 102 976 0.90625 0.015 15 1 1 1.024ms to 16.384ms short open 0.96875 0.015 0.5 ? v + t out (seconds) 699512 f02 1000 10000 100 10 1 0.001 0.1 0.01 increasing v div v + 0v pol bit = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pol bit = 1 figure 2. frequency range and pol bit vs divcode 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
11 t out 1/2 t out rst out LTC6995-1 t rst t width out remains high while rst is high t out 1/2 t out out ltc6995-2 t rst t width out remains high while rst is low rst 699512 f04 t out 1/2 t out rst out LTC6995-1 t rst t width out remains low while rst is high t out 1/2 t out out ltc6995-2 t rst t width out remains low while rst is low rst 699512 f03 o pera t ion reset and polarity bit functions the reset input, rst for the LTC6995-1 and rst for the ltc6995-2, forces the output to a fixed state and resets the internal clock dividers. the output state when reset is determined by the polarity bit as selected by through the divcode setting. output (oscillator start state) rst/rst polarity LTC6995-1 ltc6995-2 0 0 oscillating (low) 0 (reset) 1 0 0 (reset) oscillating (low) 0 1 oscillating (high) 1 (reset) 1 1 1 (reset) oscillating (high) with the pol bit programmed to be 0, the output will be forced low when reset. when reset is released by chang- ing state , the oscillator starts. the next rising edge at the output follows a precise half cycle delay. with the pol bit programmed to be 1, the output will be for ced high when reset. when reset is released by chang - ing state , the oscillator starts. the next falling edge at the output follows a precise half cycle delay. figure 3. reset timing diagram (pol bit = 0) figure 4. reset timing diagram (pol bit = 1) 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
12 changing divcode after start-up following start-up, the a/d converter will continue moni- toring v div for changes. the ltc6995 will respond to divcode changes in less than one cycle. t divcode < 500 ? t master < t out the output may have an inaccurate pulse width during the frequency transition. but the transition will be glitch-free and no high or low pulse can be shorter than the mas - ter clock period. a digital filter is used to guarantee the divcode has settled to a new value before making changes to the output. start-up time when power is first applied, the power-on reset (por) circuit will initiate the start-up time, t start . a supply voltage of typically 1.4v (1.2 v to 1.5 v over temperature) initiates the start-up sequence. the out pin is held low during this time. the typical value for t start ranges from 0.5ms to 8 ms depending on the master oscillator frequency (independent of n div ): t start( typ ) = 500 ? t master during start-up, the div pin a/d converter must deter- mine the correct divcode before the output is enabled. the start -up time may increase if the supply or div pin voltages are not stable. for this reason, it is recommended to minimize the capacitance on the div pin so it will prop- erly track v + . less than 100 pf will not affect performance. start-up behavior when first powered up, the output is held low. if the polarity is set for non-inversion (pol = 0) and the output is enabled at the end of the start-up time, out will begin oscillating. if the output is being reset ( rst = 1 for LTC6995-1 and rst = 0 for ltc6995-2) at the end of the start-up time, it will remain low due to the pol bit = 0. when reset is released the oscillator starts and the output remains low for precisely one half cycle of the programmed period. in inverted operation (pol = 1), the start-up sequence is similar. however, the ltc6995 does not know the correct divcode setting when first powered up, so the output defaults low. at the end of t start , the value of divcode is recognized and out goes high ( inactive) because pol = 1. if the output is being reset ( rst = 1 for LTC6995-1 and rst = 0 for ltc6995-2) at the end of the start-up time, it will remain high due to the pol bit = 1. when reset is released the oscillator starts and the output remains high for precisely one half cycle of the programmed period. figures 7 to 10 detail the possible start-up sequences. div 200mv/div out 1v/div 10ms/div 699512 f05 v + = 3.3v r set = 200k v + 1v/div out 1v/div 250s/div 699512 f06 v + = 2.5v divcode = 15 r set = 50k 500s figure 5. divcode change from 1 to 0 figure 6. typical start-up LTC6995-1 with rst = 0v o pera t ion 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
13 figure 7. start-up timing diagram (reset = 0, pol bit = 0) figure 8. start-up timing diagram (reset = 1, pol bit = 0) figure 9. start-up timing diagram (reset = 0, pol bit = 1) figure 10. start-up timing diagram (reset = 1, pol bit = 1) o pera t ion t out LTC6995-1 t start 1/2 t out rst out t out ltc6995-2 t start 1/2 t out rst out 699512 f07 t out ltc6995-2 t start 1/2 t out rst out t out LTC6995-1 t start 1/2 t out rst out 699512 f08 t out LTC6995-1 t start 1/2 t out rst out t out ltc6995-2 t start 1/2 t out rst out 699512 f09 t out ltc6995-2 t start 1/2 t out rst out rst out t out LTC6995-1 t start 1/2 t out 699512 f10 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
14 a pplica t ions i n f or m a t ion basic operation the simplest and most accurate method to program the ltc6995 is to use a single resistor, r set , between the set and gnd pins. the design procedure is a 3-step process. first select the pol bit setting and n div value, then calculate the value for the r set resistor. step 1: select the ltc6995 version and pol bit setting determine if the application requires an active- high, LTC6995-1 or active- low, ltc6995-2 reset function. otherwise the two versions share identical functionality. the out pin polarity depends on the setting of the pol bit. to force out = 0 during reset, choose pol bit = 0. to force out = 1 during reset, choose pol bit = 1. step 2: select the n div frequency divider value as explained earlier, the voltage on the div pin sets the divcode which determines both the pol bit and the n div value. for a given output clock period, n div should be selected to be within the following range. t out 16.384ms n div t out 1.024ms (1) to minimize supply current, choose the lowest n div value ( generally recommended). alternatively, use table 1 as a guide to select the best n div value for the given application. with pol already chosen, this completes the selection of divcode. use table 1 to select the proper resistor divider or v div /v + ratio to apply to the div pin. step 3: calculate and select r set the final step is to calculate the correct value for r set using the following equation. r set = 50k 1.024ms ? t out n div 1 (2) select the standard resistor value closest to the calculated value. example: design a 1 hz oscillator with minimum power consumption, an active-high reset input, and the out pin low during reset. step 1: select the ltc6995 version and pol bit setting for active-high reset select the LTC6995-1. for out low during reset choose pol bit = 0. step 2: select the n div frequency divider value choose an n div value that meets the requirements of equation (1), using t out = 1000ms: 61.04 n div 976.6 potential settings for n div include 64 and 512. n div = 64 is the best choice, as it minimizes supply current by us- ing a large r set resistor. pol = 0 and n div = 64 requires divcode = 2. using table 1, choose r1 = 976 k and r2 = 182k values to program divcode = 2. step 3: select r set calculate the correct value for r set using equation (2). r set = 50k 1.024ms ? 1000ms 64 = 763k since 763 k is not available as a standard 1% resistor, substitute 768 k if a C0.7% frequency shift is acceptable. otherwise, select a parallel or series pair of resistors such as 576k + 187k to attain a more precise resistance. the completed design is shown in figure 11. divcode = 2 699512 f11 LTC6995-1 rst gnd set rst out v + div r1 976k r2 182k r set 763k 2.25v to 5.5v figure 11. 1hz oscillator 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
15 a pplica t ions i n f or m a t ion power-on reset (por) function when power is applied to the ltc6995 the output is held low for t start , then takes on the value of the pol bit as the clock cycle begins. if pol = 0 (divcode < 8) the output will remain low for a programmable interval of t start + 1/2 t out , assuming the rst pin is inactive. this makes the ltc6995 useful as a programmable long-time power-on reset ( por), with the low output used to hold a system in reset for a fixed period after power is applied. timing begins when the v + supply exceeds approximately 1.4v. to prevent additional output transitions after the initial por time, the oscillator can be disabled by removing the set pin current. this prevents the internal master oscillator output from clocking the frequency dividers or output, while keeping it biased so it can resume operation quickly. the easiest way to implement this feature is to connect r set between the set and out pins. figure 12 shows the basic power-on reset function. when the half cycle times out, the output goes high, eliminates the set pin current, and stops additional out pin transi - tions. the output remains high until the device is reset by driving the rst input or power is cycled off then back on. the por interval is only one half of an oscillator period so component selection is slightly different. table 2 provides the component values required for one half cycle time intervals. timing starts after a short startup delay time following the application of the v + supply. LTC6995-1 t por = 1 second for values shown pol = 0 divcode = 3 ndiv = 512 rst = v + for ltc6995-2 rst gnd set out v + div r set 191k r2 280k r1 1m 0.1f 2.25v to 5.5v por out pol = 0 699512 f12 t delay (1/2 t out ) t start timer stopped ~1.4v starts timer power-on reset v + figure 12. active low power-on reset (1 second interval example) table 2. power-on reset (por). one shot, one half cycle delay programming output low during time interval, pol = 0 divcode t delay time interval (1/2 t out ) r1 (k) r2 (k) ~r set (k) 0 512s to 8.2ms open short t delay(ms) ? 97.6 1 4.1ms to 65.5ms 976 102 t delay(ms) ? 12.2 2 32.8ms to 524.3ms 976 182 t delay(ms) ? 1.5 3 262.1ms to 4.2sec 1000 280 t delay(sec) ? 190.7 4 2.1sec to 33.6sec 1000 392 t delay(sec) ? 23.8 5 16.8sec to 4.5min 1000 523 t delay(min) ? 178.6 6 2.2min to 35.8min 1000 681 t delay(min) ? 22.7 7 17.9min to 4.8hrs 1000 887 t delay(hr) ? 167.6 note: power-on reset time = t delay + t start 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
16 a pplica t ions i n f or m a t ion for shorter power-on reset times (1 ms to 73 ms) the timer startup delay becomes a significant part of the total por time. to take this delay into account the value for r set can be modified from the values shown in table 2. for a por time in the range from 1 ms to 16ms (divcode = 0), r set should be t por (ms) ? 49.5. for a por time in the range from 4.5 ms to 73ms (divcode = 1), r set is t por (ms) ? 10.9. for longer por times (divcode 2 through 7) the startup time is insignificant. after power on, the delay fol - lowing a reset condition will be in the same range as shown for t delay in table 2 for these two divcode selections. for short por times, a more precise estimation of the startup time can be found from the following: t start (s) = 256 + 16 ?(12 Cdivcode) ( ) r set (k ? ) 50 + 80 supply bounce resets the internal timer so the por circuit automatically debounces supply noise. por timing starts from the time that the v + supply has reached approximately 1.4 volts. long timer one shots and delay generators the por circuit of figure 12 is also useful when the reset inputs are driven. this creates edge triggered timing events that are active low and can either be re-triggered or can stop after one programmed interval. the programmed time interval can range from only 500 s to over 4 hours with just resistor value changes. the circuits in figure 13 show how a por or active low interval can be re- started to provide a full system reset time. the figure 14 circuit requires an indication from the system being reset that it is ready before timing out. the ltc6995-2 can accommodate an active high ok signal. by forcing a reset condition at power on the ltc6995 can be used to create a long time delayed rising edge triggered by either a falling edge signal ( LTC6995-1) or a rising edge signal (ltc6995-2) as show in figure 15. figure 13. system resets on command with full por time interval. reset pulse is debounced automatically LTC6995-1 active high reset rst gnd set out v + div r set 100k r2 r1 0.1f v + v + por out pol = 0 rst t start + 1/2 t out 1/2 t out timer stopped timer stopped reset por por v + ltc6995-2 active low reset rst gnd set out v + div r set 100k r2 r1 0.1f v + v + por out pol = 0 rst 699512 f13 t start + 1/2 t out 1/2 t out timer stopped timer stopped reset por por v + 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
17 a pplica t ions i n f or m a t ion figure 14. extended por. timer reset during initial por interval. full por interval provided once system signals the ok figure 15. long time delayed rising edge. delay time can range from 500s to 4.8 hours LTC6995-1 system rst gnd set out v + div r set r2 r1 0.1f v + por 699512 f14 out pol = 0 rst t start + 1/2 t out 1/2 t out timer stopped system ok system ok por por extended por v + ltc6995-2 output rising edge triggered pol = 0 trigger rst gnd set out v + div r set r2 r1 0.1f v + 699512 f15 output trigger 1/2 t out 1/2 t out v + 1/2 t out 1/2 t out LTC6995-1 output falling edge triggered pol = 0 trigger rst gnd set out v + div r set r2 r1 0.1f v + output trigger v + 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
18 a pplica t ions i n f or m a t ion watchdog timers using the same circuits as shown in figure 15 with pe- riodic pulsing of the reset input can create an effective watchdog timer. a watchdog pulse is required from a system within each timing interval. the watchdog timeout interval can be programmed from 500 s to 4.8 hours. if a pulse is missed the output goes high to indicate that the system software may be caught in an infinite loop. this high level can be used to initiate software diagnostic or restart procedures. the ltc6995 internal clock stops and the output remains high until the software recovers and returns to issuing watchdog pulses. figure 16 shows the timing for this application. watchdog timers are used to detect if a system operating software is diverted from the designed program sequence for any reason. it is always a possibility that the software could get stuck in a way that keeps the watchdog pulse in the state that holds the timer in the reset so it can never time out. in this condition the watchdog timer is ineffective and will never force corrective action. to help to prevent this a second one shot can be used to reset the watchdog timer as shown in figure 17. figure 16. watchdog timer. same circuits as shown in figure 15 figure 17. extra-reliable watchdog timer. allows timeout if system watchdog pulse gets stuck in the timer reset state. both timer devices can share the same divcode setting 699512 f16 output rst (LTC6995-1) rst (ltc6995-2) service watchdog missed pulse watchdog pulses resume timeout timer restarts v + LTC6995-1 output falling edge triggered pol = 0 divcode = 1 rst gnd set out v + div r set 604k r2 102k r1 976k 0.1f v + 699512 f17 ltc6993-1 rising edge triggered positive output pulse divcode = 1 50ms watchdog timer 100s one shot system positive watchdog pulse trg gnd set out v + div r set 619k v + 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
19 a pplica t ions i n f or m a t ion figure 18. gated oscillators. first one-half cycle time always accurate gated oscillators the reset input ( rst) clears all internal dividers so that, when released, the output will start clocking with a full programmed period. this edge can be used to gate the output on and off at a known starting point for the clock. circuits which count clock cycles for further timing pur - poses will always have an accurate count of full cycles until reset. the output clock is always at 50% duty cycle and the period of each cycle can range from 1 ms to 9.5 hours. depending on the polarity bit selection the output clock can start high or low as shown in figure 18. self-resetting circuits the rst pin has hysteresis to accommodate slow- changing input voltages. furthermore, the trip points are proportional to the supply voltage ( see note 6 and the rst threshold voltage vs supply voltage curve in typical performance characteristics). this allows an rc time constant at the rst input to generate a delay that is nearly independent of the supply voltage. 699512 f18 out pol = 0 out pol = 1 1/2 t out 1/2 t out rst ltc6995-2 active low reset rst rising edge starts the clock out pol = 0 out pol = 1 1/2 t out 1/2 t out rst LTC6995-1 active high reset rst falling edge starts the clock a simple application of this technique allows the ltc6995 output to reset itself, producing a well-controlled pulse once each cycle. figures 19 a and 19 b show circuits that produce approximately 1 s pulses once a minute. the only difference is the version of ltc6995 used and the pol bit setting, which controls whether the pulse is positive or negative. voltage controlled frequency with one additional resistor, the ltc6995 output frequency can be manipulated by an external voltage. as shown in figure 20, voltage v ctrl sources/sinks a current through r vco to vary the i set current, which in turn modulates the output frequency as described in equation (3). f mhzk nr r r v v out div vco vco se t ct rl s =+ 15 0 1024 1 ? ? e et ? ? ? ? ? ? (3) 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
20 digital frequency control the control voltage can be generated by a dac ( digital- to-analog converter), resulting in a digitally-controlled frequency. many dacs allow for the use of an external reference. if such a dac is used to provide the v ctrl voltage, the v set dependency can be eliminated by buffer- ing v set and using it as the dacs reference voltage, as shown in figure 21. the dacs output voltage now tracks any v set variation and eliminates it as an error source. the set pin cannot be tied directly to the reference input of the dac because the current drawn by the dacs ref input would affect the frequency. i set extremes (master oscillator frequency extremes) when operating with i set outside of the recommended 1.25a to 20 a range, the master oscillator operates outside of the 62.5 khz to 1 mhz range in which it is most accurate. the oscillator can still function with reduced accuracy for i set < 1.25 a . at approximately 500 na, the oscillator output will be frozen in its current state. the output could halt in a high or low state. this avoids introducing short pulses when frequency modulating a very low frequency output. at the other extreme , it is not recommended to operate the master oscillator beyond 2 mhz because the accuracy of the div pin adc will suffer. a pplica t ions i n f or m a t ion LTC6995-1 2.25v to 5.5v 0.1f out r1 1m r2 523k r set 178k rst gnd set out v + div c pw 470pf r pw 2.26k 699512 f19a 60 seconds 1s pulse width v rst(rising) v + t pulse = ?r pw ? c pw ? in t pulse C2.26k ? 470pf ? in(1 C 0.61) t pulse 1s 1? ( ) ltc6995-2 2.25v to 5.5v 0.1f 699512 f19b out r1 523k r2 1m 60 seconds 0.9s pulse width v rst(falling) v + t pulse = ?r pw ? c pw ? in t pulse C2.26k ? 470pf ? in(0.43) t pulse 0.9s r set 178k rst gnd set out v + div c pw 470pf r pw 2.26k ( ) 699512 f20 LTC6995-1 rst gnd set out v + div r1 c1 0.1f r2 r set r vco v ctrl v + figure 19a. self-resetting circuit (divcode = 5) figure 19b. self-resetting circuit (divcode = 10) figure 20. voltage-controlled oscillator 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
21 frequency modulation and settling time the ltc6995 will respond to changes in i set up to a C3 db bandwidth of 0.4 ? f out . following a 2 or 0.5 step change in i set , the output frequency takes less than one cycle to settle to within 1% of the final value. power supply current the power supply current varies with frequency, supply voltage and output loading. it can be estimated under any condition using the following equation. this equation ignores c load ( valid for c load < 1 nf) and assumes the output has 50% duty cycle. i s(typ) v + ? f master ? 7.8pf + v + 420k ? + v + 2 ?r load + 1.8 ?i set + 50a supply bypassing and pcb layout guidelines the ltc6995 is a 2.2% accurate silicon oscillator when used in the appropriate manner. the part is simple to use a pplica t ions i n f or m a t ion ? + 699512 f21 LTC6995-1 rst gnd set out v + div c1 0.1f r1 r2 r set v + r vco v + 0.1f 1/2 ltc6078 ltc1659 v + v cc ref gnd v out p d in clk cs/ld 1mhz 50k 1024 n div r vco f out = d in = 0 to 4095 1 + ? r vco r set d in 4096 ( ) 0.1f figure 21. digitally-controlled oscillator and by following a few rules, the expected performance is easily achieved. adequate supply bypassing and proper pcb layout are important to ensure this. figure 22 shows example pcb layouts for both the tsot-23 and dfn packages using 0603 sized passive components. the layouts assume a two layer board with a ground plane layer beneath and around the ltc6995. these layouts are a guide and need not be followed exactly. 1. connect the bypass capacitor, c1, directly to the v + and gnd pins using a low inductance path. the connection from c1 to the v + pin is easily done directly on the top layer. for the dfn package, c1s connection to gnd is also simply done on the top layer. for the tsot-23, out can be routed through the c1 pads to allow a good c1 gnd connection. if the pcb design rules do not allow that, c 1 s gnd connection can be accomplished through multiple vias to the ground plane. multiple vias for both the gnd pin connection to the ground plane and the c1 connection to the ground plane are recommended to minimize the inductance. capacitor c1 should be a 0.1f ceramic capacitor. 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
22 2. place all passive components on the top side of the board. this minimizes trace inductance. 3. place r set as close as possible to the set pin and make a direct, short connection. the set pin is a current summing node and currents injected into this pin directly modulate the operating frequency. having a short connection minimizes the exposure to signal pickup. 4. connect r set directly to the gnd pin. using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. use a ground trace to shield the set pin. this provides another layer of protection from radiated signals. 6. place r1 and r2 close to the div pin. a direct, short connection to the div pin minimizes the external signal coupling. 699512 f22 LTC6995-1 rst gnd set out v + div c1 0.1f r1 r2 r set v + v + div set out gnd rst c1 r1 r2 v + r set dfn package rst gnd set out v + div r2 v + r set tsot-23 package r1 c1 figure 22. supply bypassing and pcb layout a pplica t ions i n f or m a t ion 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
23 typical a pplica t ions timed power switches, auto shutoff after one hour LTC6995-1 active high reset 1/2 t out = 1 hour rst gnd set out v + div r set 169k 100k r2 887k r1 1m 0.1f 5v 5v push to activate low = on high = off 699512 ta08 v in gnd ctl sense gate stat ltc4412hv p-channel mosfet 3v to 36v 2.6v to 5.5v c out * to load current depends on pmos selection *drain-source diode of mosfet 0.1f in gnd ctl out stat ltc4411 to load up to 2.6a c out 4.7f 1f 5 second on/off timed relay driver r1 1m r4 10k run reset d1 1n4148 12v no coto 1022 relay 9001-12-01 l c2 0.1f 0.1f q1 2n2219a r2 392k 699512 ta02 r3 118k 5v relay enable c 1 LTC6995-1 rst gnd set out v + div 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
24 typical a pplica t ions 1.5ms radio control servo reference pulse generator reset = open run = gnd 20ms frame rate generator 1.5ms reference pulse 5v 20ms period 5v r4 976k r7 10k c1 0.01f r5 102k r6 121k 1.5ms pulse 699512 ta03 LTC6995-1 rst gnd set out v + div 5v r1 1m c2 0.1f r2 280k r3 146k ltc6993-1 trig gnd set out v + div cycling (10 seconds on/off) symmetrical power supplies r8 1m r2 1k r11 5k r3 50k r6 20k ?15v in ?15v out c1 0.1f r9 392k r1 100k m4 si4435dy m3 si9410 m1 si9410 15v in 15v out m2 si4435dy 699512 ta04 r10 237k 5v LTC6995-1 rst gnd set out v + div isolated ac load flasher LTC6995-1 gnd set r set 237k v + 0.1f 5v 5v rst 5 2 10 seconds on/off 6 6 4 2 1 4 3 1 out div r3 10k open = off gnd = on r2 392k r5 5.94k u3 nte5642 isolation barrier = 7500v hot 117v ac neutral ac r6 10k r4 215 r1 1m c2 0.022f zero crossing u2 moc3041m r7 100 40w lamp 699512 ta05 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
25 typical a pplica t ions interval (wiper) timer LTC6995-1 0.1f 2s 2s 5s 5s 15s 30s 1m 2m 4m 4m off 24.9k 178k 59k 90.9k 29.4k 1m v + rst gnd set out v + div ltc6993-1 0.1f output 1m t interval 2 seconds to 4 minutes v + 2s trig gnd set out v + div 681k 699512 ta06 383k 2s 2s 5s 15s 30s 5v 1m 2m 4m off v + 15s 30s 1m 2m off 280k 113k 133k 154k adjustable time lapse photography intervalometer ltc6993-3 output non-retriggerable one shot timer 0.3s to 30s exposure time time lapse time lapse shutter open time lapse trg gnd set out v + div 56.2k 1m 681k v + 699512 ta09 LTC6995-1 long timer 3s to 3hrs rst gnd set out v + div v + 0.1f 887k 1m 0.3s to 3s 3s to 30s 523k 681k 967k 30s to 3m 3m to 30m 30m to 3hrs 3s to 30s 2m 1m long short 66.5k 1m 2m long short 392k 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
26 please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. p ackage descrip t ion 3.00 0.10 (2 sides) 2.00 0.10 (2 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (tbd) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 1.35 0.10 (2 sides) 1 3 64 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dcb6) dfn 0405 0.25 0.05 0.50 bsc pin 1 notch r0.20 or 0.25 45 chamfer 0.25 0.05 1.35 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.70 0.05 3.55 0.05 package outline 0.50 bsc dcb package 6-lead plastic dfn (2mm 3mm) (reference ltc dwg # 05-08-1715 rev a) 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 ma x 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
27 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 09/13 grammatical corrections correction to master oscillator, block diagram divcode changed from 4 to 5, figure 19a divcode changed from 11 to 10, figure 19b ltc6995 block identified as LTC6995-1, figure 21 and figure 22 replace v + with 5v, sentry time schematic 1, 4, 8, 16 8 20 20 21, 22 28 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2
28 ? linear technology corporation 2013 lt 0913 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC6995-1 r ela t e d p ar t s typical a pplica t ion part number description comments ltc1799 1mhz to 33mhz thinsot silicon oscillator wide frequency range ltc6900 1mhz to 20mhz thinsot silicon oscillator low power, wide frequency range ltc6906 / ltc6907 10khz to 1mhz or 40khz thinsot silicon oscillators micropower, i supply = 35a at 400khz ltc6930 fixed frequency oscillator, 32.768khz to 8.192mhz 0.09% accuracy, 110s start-up time, 105a at 32khz ltc6990 timerblox: voltage-controlled silicon oscillator fixed-frequency or voltage-controlled operation ltc6991 timerblox: very low frequency oscillator with reset cycle time from 1ms to 9.5 hours, no capacitors, 2.2% accurate ltc6992 timerblox: voltage-controlled pulse width modulator ( pwm ) simple pwm with wide frequency range ltc6993 timerblox: monostable pulse generator (one shot) resistor programmable pulse width of 1s to 34sec ltc6994 timerblox: delay block/debouncer delays rising, falling or both edges 1s to 34sec sentry timer 699512 ta07 r2 49.9k 60.4k 800hz alarm tone divcode = 0 4 hour timer divcode = 7 push button every 4 hours or alarm sounds ltc6995-2 rst gnd set out v + div ff q clk clr q d 100k r1 887k 5v 5v 5v 5v 75k 332k 15 32 699512fa for more information www.linear.com/LTC6995-1 LTC6995-1/ltc6995-2

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